The AD800 employ second order phase-locked loop architecture to perform clock recovery and data re timing on non-return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20Mbps and 160Mbps. The products described here have been defined to work with standard telecommunications bit rates. 45Mbps DS-3 and 52Mbps STS-1 are supported by AD800-45 and AD800-52 respectively. 155Mbps STS-3 or STM-1 are supported by the AD802-155.

Unlike other PLL-based clock recovery circuits, these devices do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data. The phase-lock loop than acquires the phase of the input data, and ensures the phase of the output signals track changes in the phase of the output data. The loop damping of the circuit is dependent of the value of user selected capacitor, this defines jitter peaking and performance and impacts acquisition time. The devices exhibit 0.08 dB jitter peaking, and acquire lock on random or scrambled data within 4 x 105 bit periods when using damping factor of 5.