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Mixed Signal Front-end Baseband Transceiver for Broadband Applications, 80 MSPS Version

Model: AD9861-80

  • Receive path includes dual 10-bit analog-to-digital converters with internal/external reference, 50 and 80 MSPS versions
  • Transmit path includes dual 10-bit, 200 MSPS digital-to-analog converters with 1x, 2x, Or 4x interpolation and programmable gain control
  • Internal clock distribution block includes programmable phase-locked-loop and timing generation circuitry allowing single reference clock operation
  • 20-bit flexible I/O data interface allow various interleaved/non-interleaved data transfers in half-duplex mode and interleaved data transfers in full-duplex mode
  • Configurable through SPI compliant port or MODE selection pins
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The AD9861 is a member of the MxFE® family, a group of integrated converters for communications market. AD9861 includes dual 10-bit analog-to-digital converters (ADCs) and dual 10-bit digital-to-analog converters (TxDAC® converters). Two speed grades are available, a -50 and -80. The -50 is optimized for ADC sampling of 50 MSPS and less, while the -80 is optimized for ADC sample rates between 50 MSPS and 80 MSPS. The dual TxDAC converters operate at speeds up to 200MHz and includes a bypassable 2x or 4x interpolation filter. Three auxiliary converters are also available to provide required system level control voltages or monitor system signals. All devices are optimized for low power, small form factor and provide a cost effective solution for the broadband communication market.

The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The ADCs and TxDAC Converters clock are generated within timing generation block which utilizes user programmable options such as divide circuits, PLL multiplier and switches.

Flexible bi-directional 20-bit I/O bus is used to accommodate a variety of custom digital back ends or open market DSPs. In half duplex systems, interface supports 20-bit parallel transfers or 10-bit interleaved transfers. In Full duplex systems, the interface supports an interleaved 10-bit ADC bus and an interleaved 10-bit Tx bus. The flexible I/O bus reduces pin count and therefore required package size.

The AD9861 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate ADC in low power mode, configure the TxDAC converter interpolation rate, control the ADC power down and TxDAC power down. The SPI allows for more programmable options for both TxDAC path (for example, coarse and fine gain control, offset control for channel matching) and ADC path (for example, internal duty cycle stabilizer, 2’s complement data format).

The AD9861 is packaged in a 64-pin lfCSP package (low profile, fine pitch chip scale package). The 64-pin lfCSP package footprint is only 9 mm by 9 mm and is less than 0.9mm high fitting into tightly spaced applications such as PCMCIA cards.

  • Receive path includes dual 10-bit analog-to-digital converters with internal/external reference, 50 and 80 MSPS versions
  • Transmit path includes dual 10-bit, 200 MSPS digital-to-analog converters with 1x, 2x, Or 4x interpolation and programmable gain control
  • Internal clock distribution block includes programmable phase-locked-loop and timing generation circuitry allowing single reference clock operation
  • 20-bit flexible I/O data interface allow various interleaved/non-interleaved data transfers in half-duplex mode and interleaved data transfers in full-duplex mode
  • Configurable through SPI compliant port or MODE selection pins
  • Independent Rx and Tx Powerdown control pins
  • 64 Lead lfCSP package (9mm x 9mm footprint)
  • 3 configurable auxiliary converter pins
  • Applications:
    • Broadband access
    • Broadband LAN
    • Communications (Modems)
 
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