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Mixed Signal DSP Controller, Multiple Boot Modes

Model: ADSP-21990

  • External memory interface
  • Dedicated memory DMA controller for data/instruction transfer between internal/external memory
  • Programmable PLL and flexible clock generation circuitry enables full speed operation from low speed input clocks
  • IEEE JTAG Standard 1149.1 test access port supports on-chip emulation and system debugging
  • 8-channel, 14-bit analog-to-digital converter system, with up to 20 MSPS sampling rate (at 160 MHz core clock rate)
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The ADSP-21990 is a mixed-signal DSP controller based on the ADSP-2199x DSP core, suitable for a variety of high performance industrial motor control and signal processing applications that require the combination of a high performance DSP and the mixed-signal integration of embedded control peripherals such as analog-to-digital conversion. Target applications include industrial motor drives, uninterruptible power supplies, optical networking control, data acquisition systems, test and measurement systems, and portable instrumentation.

The ADSP-21990 integrates the fixed-point ADSP-2199x family- based architecture with a serial port, an SPI-compatible port, a DMA controller, three programmable timers, general-purpose programmable flag pins, extensive interrupt capabilities, onchip program and data memory spaces, and a complete set of embedded control peripherals that permits fast motor control and signal processing in a highly integrated environment.

The ADSP-21990 integrates the fixed-point ADSP-2199x family- based architecture with a serial port, an SPI-compatible port, a DMA controller, three programmable timers, general-purpose programmable flag pins, extensive interrupt capabilities, onchip program and data memory spaces, and a complete set of embedded control peripherals that permits fast motor control and signal processing in a highly integrated environment.

  • External memory interface
  • Dedicated memory DMA controller for data/instruction transfer between internal/external memory
  • Programmable PLL and flexible clock generation circuitry enables full speed operation from low speed input clocks
  • IEEE JTAG Standard 1149.1 test access port supports on-chip emulation and system debugging
  • 8-channel, 14-bit analog-to-digital converter system, with up to 20 MSPS sampling rate (at 160 MHz core clock rate)
  • 3-phase, 16-bit, center-based PWM generation unit with 12.5ns resolution at 160 MHz core clock (CCLK) rate
  • Dedicated 32-bit encoder interface unit with companion encoder event timer
  • Dual 16-bit auxiliary PWM outputs
  • 16 general-purpose flag I/O pins
  • 3 programmable 32-bit interval timers
  • SPI communications port with master or slave operation
 
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