The ADSP-21992 is a mixed-signal DSP controller based on the
ADSP-2199x DSP core, suitable for a variety of high performance
industrial motor control and signal processing applications that require the combination of a high performance DSP and the mixed-signal integration of embedded control peripherals, such as analog-to-digital conversion with communications interfaces such as CAN. Target applications include industrial motor drives, uninterruptible power supplies, optical networking control, data acquisition systems, test and measurement Systems, and portable instrumentation.
The ADSP-21992 integrates the fixed-point ADSP-2199x family based architecture with a serial port, an SPI-compatible port, a DMA controller, three programmable timers, general-purpose programmable flag pins, extensive interrupt capabilities, onchip program and data memory spaces, and a complete set of embedded control peripherals that permits fast motor control and signal processing in a highly integrated environment.
The ADSP-21992 architecture is code compatible with previous ADSP-217x-based ADMCxxx products. Although the architectures are compatible, the ADSP-21992, with ADSP-2199x
architecture, has a number of enhancements over earlier architectures. The enhancements to computational units, data
address generators, and program sequencer make the ADSP-21992 more flexible and easier to program than the previous ADSP-21xx embedded DSPs.
Indirect addressing options provide addressing flexibility—premodify with no update, pre- and post-modify by an immediate 8-bit, twos complement value and base address registers for easier implementation of circular buffering.
- ADSP-2199x, 16-bit, fixed-point DSP core with up to 160MIPS sustained performance
- 48K words of on-chip RAM, as 32K words on-chip 24-bit program RAM, and 16K words on-chip, 16-bit data RAM
- External memory interface
- Dedicated memory DMA controller for data/instruction transfer between internal/external memory
- IEEE JTAG Standard 1149.1 test access port supports on-chip
emulation and system debugging
- 8-channel, 14-bit analog-to-digital converter system, with up
to 20 MSPS sampling rate (at 160 MHz core clock rate)
- 3-phase 16-bit center based PWM generation unit with 12.5ns resolution at 160 MHz core clock (CCLK) rate
- Dedicated 32-bit encoder interface unit with companion
encoder event timer
- Dual 16-bit auxiliary PWM outputs
- 16 general-purpose flag I/O pins
- 3 programmable 32-bit interval timers
