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Single-core SHARC+ ARM Cortex-A5 Processor with 1MB Shared L2, 10/100 Ethernet and 176-LQFP

Model: ADSP-SC570

  • Dual-enhanced SHARC+ high performance floating-point cores
  • Up to 500MHz per SHARC+ core
  • Up to 3Mb (384kB) L1 SRAM memory per core with parity (optional ability to configure as cache)
  • 32-bit, 40-bit and 64-bit floating-point support
  • 32-bit fixed point
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The ADSP-SC57x/ADSP-2157x processors are members of the SHARC® family of products. The ADSP-SC57x processor is based on the SHARC+® dual-core and the ARM® Cortex®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high-performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

  • Dual-enhanced SHARC+ high performance floating-point cores
  • Up to 500MHz per SHARC+ core
  • Up to 3Mb (384kB) L1 SRAM memory per core with parity (optional ability to configure as cache)
  • 32-bit, 40-bit and 64-bit floating-point support
  • 32-bit fixed point
  • Byte, short word, word, long word addressed
  • ARM Cortex-A5 core
  • 500MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle
  • 32kB L1 instruction cache with parity/32kB L1 data cache with parity
  • 256kB L2 cache with parity
  • Powerful DMA system
  • On-chip memory protection
  • Integrated safety features
  • Low system power across automotive temperature range
 
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